The present invention generally relates to techniques for making engineering changes in the wiring between semiconductor device chips carried on the same substrate and, more particularly, to the use of interposer chips mounted between the device chips and the substrate for making such changes.
As discussed in copending patent application Ser. No. 792,708, filed Oct. 28, 1985 in the name of Charles T. Ryan, for "Method and Structure for Effecting Engineering Changes in a Multiple Device Module Package" and assigned to the present assignee, it is the practice in modern packaging technology to mount many integrated circuit chip devices on a common substrate which interconnects the devices with each other and to I/O's at the end or on the opposite surface of the substrate. Such substrates normally are constructed of layered green ceramic sheets having thousands of vias and printed lines that form the internal circuit network. After the substrate has been laminated and sintered, there is no practical method of changing the buried internal network. However, it becomes necessary quite frequently to modify the internal circuitry to (1) correct defective lines and/or vias and (2) make changes in the basic circuitry to accommodate design changes to upgrade the package or modify it by the use of different devices or the like.
As further discussed in said copending patent application, a number of engineering change (EC) schemes have been developed to modify the interconnection network between device chips, i.e., to disrupt the unwanted part of the network and to substitute a replacement network part. In known schemes, the network disruptions and replacements are accomplished through the use of "fan-out" networks with or without EC pads that are physically located in spaces between the device chips along the surface of the substrate on which the device chips are mounted. Such spaces prevent the device chips from being arranged with maximum packing density on the substrate with the result that circuit path length in the interchip network is undesirably lengthened, with attendant performance penalty. This penalty remains to be more fully addressed, although some progress has been made in reducing performance delays, due to inductance in the replacement network, by the use of chip metalization techniques rather than the use of discrete wires. Examples of such progress are disclosed in the aforesaid copending patent application and in the IBM.RTM. Technical Disclosure Bulletin paper, "Interposed Segmented Chip Carrier" by J. M. Harvilchuck et al., Vol. 27, No. 8, January 1985, page 4672. It is to be noted, however, that the cited Technical Disclosure Bulletin does not provide a full engineering change capability in that only changes in the chip signal redistribution network pattern are relatively easily made. Any change required in substrate wiring would necessitate the costly and time-consuming fabrication of a new substrate. This would be the case, for example, where a new network is to be added, an additional load is to be added to an existing network or a network is to be rerouted.